The present invention is directed to a method of fabricating integrated circuits (ICs) and, in particular to a method of fabricating a polysilicon to polysilicon, i.e., poly-poly, capacitor on a BiCMOS device utilizing a field effect transistor (FET) gate layer and a bipolar SiGe extrinsic base polysilicon layer to form the base plates of the capacitor. More specifically, the present invention is directed to a method for fabricating a poly-poly capacitor utilizing process steps and structures which are used to form the gate of the metal oxide semiconductor (MOS) transistor and the base structure of the bipolar transistor in a BiCMOS (i.e., bipolar device and complementary metal oxide semiconductor (CMOS) device) process.
In the field of semiconductor device manufacturing, CMOS (complementary metal oxide semiconductor) and BiCMOS (bipolar device and complementary metal oxide semiconductor) technologies have been widely used for integrating highly complex analog-digital subsystems onto a single chip. In such subsystems, high precision capacitors are typically required.
Several types of capacitors are available including diffusion-poly capacitors, poly-poly capacitors and metal-metal capacitors. In order to meet the demand for high precision capacitors in today""s generation of integrated devices, poly-poly capacitors have been increasingly used.
Despite its high precision, a poly-poly capacitor is a compromise between high cost and ideal capacitor characteristics since it is relatively easy to construct, and has electrical characteristics better than diffusion-poly capacitors, but inferior electrical characteristics to metal-metal capacitors. However, metal-metal capacitors are much more difficult to fabricate than are poly-poly capacitors. Thus, poly-poly capacitors are the ever increasing choice used in the semiconductor industry for manufacturing integrated circuits in BiCMOS processes.
U.S. Pat. No. 5,195,017 describes in its xe2x80x9cbackgroundxe2x80x9d section several double level polysilicon processes have been employed in fabricating poly-poly capacitors, i.e. the so-called xe2x80x9cLin EPIC double level processxe2x80x9d and the xe2x80x9c4/3 Linear processxe2x80x9d.
The Lin EPIC double level process uses a two-mask approach to define a capacitor bottom plate. The first polysilicon layer is masked and etched separate from the second polysilicon layer. Due to separate masking and etching steps, this prior art process is expensive, complicated and time consuming. Additionally, the topography that is associated with this prior art process requires an additional step of planarization prior to in depositing metal on the appropriate contact points.
In the other double level process, namely the 4/3 Linear process, a single mask is used to define the bottom plate. The first level of polysilicon serves as the bottom plate and the CMOS gate. After the interlevel dielectric is formed, the second polysilicon layer is deposited to form the capacitor top plate. In order to eliminate filaments from the bottom plate edges and the CMOS gate edges, a large overetch is required. If there is a negative slope on the bottom plate edge, filaments will be trapped under the bottom plate. Moreover, since this is a double level process, the added topography also requires additional planarization prior to metallization.
In view of the drawbacks with prior art methods of fabricating poly-poly capacitors, there is a continued need for developing a new and improved method which significantly reduces the complications and expenses associated with the prior art methods. It would be especially beneficial if a method of fabricating a poly-poly capacitor could be developed which utilizes processing steps and structures which are also used to form the gate of the MOS transistor and base structure of the bipolar transistor in a BiCMOS process since such a method would significantly reduce the number of processing steps and costs associated with manufacturing integrated circuits.
One object of the present invention is to provide a method of fabricating a poly-poly capacitor for use in CMOS or BiCMOS integrated circuits that is not complicated or expensive to manufacture.
Another object of the present invention is to provide a method of fabricating a poly-poly capacitor utilizing existing polysilicon and masking steps, thereby achieving the integration of the poly-poly capacitor into the BiCMOS device at a low cost.
A yet further object of the present invention is to provide a method of fabricating a poly-poly capacitor utilizing steps and structures that are typically used to form the gate of the MOS transistor and the base structure of the bipolar transistor in a BiCMOS process.
The foregoing and other objects are achieved by constructing a poly-poly capacitor comprising two plate electrodes, wherein at least one of the plate electrodes is composed of SiGe polysilicon, said plate electrodes being separated by an insulating layer.